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tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 1/63 ? organization of banks rate of size bk0 bk1 bk2 bk3 tc58fvm5t2a 1 3 3 1 TC58FVM5B2A 1 3 3 1 tc58fvm5t3a 3 3 1 1 tc58fvm5b3a 1 1 3 3 ? mode control compatible with jedec standard commands ? erase/program cycles 10 5 cycles typ. ? access time (random/page) v dd cl = 30 pf cl = 100 pf 2.7~3.6 v 65 ns/25 ns 70 ns/30 ns 2.3~3.6 v 70 ns/30 ns 75 ns/35 ns ? power consumption 10 a (standby) 15 ma (program/erase operation) 55 ma (random read operation) 5 ma (page read operation) 11 ma (address increment read operation) ? package tc58fvm5 ** aft: tsopi48-p-1220-0.50 (weight: 0.51 g) tc58fvm5 ** axb: p-tfbga56-0710-0.80az (weight: 0.125 g) toshiba mos digital integrated circuit silicon gate cmos 32mbit (4m 8 bits/2m 16 bits) cmos flash memory description the tc58fvm5t2a/b2a/t3a/b3a is a 33554432-bit, 3.0-v read-only electrically erasable and programmable flash memory organized as 4194304 words 8 bits or as 2097152 words 16 bits. the tc58fvm5t2a/b2a/t3a/b3 a features commands for read, program and erase operations to allow easy interfacing with microprocessors. the commands are based on the jedec standard. the program and erase operations are automatically executed in the chip. the tc58fvm5t2a/b2a/t3a/b3a also features a simultaneous read/write operation so that data can be read during a write or erase operation. features ? power supply voltage v dd = 2.3 v~3.6 v ? operating temperature ta = ? 40 c~85 c ? organization 4m 8 bits/2m 16 bits ? functions simultaneous read/write page read auto program, auto page program auto block erase, auto chip erase fast program mode/acceleration mode program suspend/resume erase suspend/resume data polling/toggle bit block protection, boot block protection automatic sleep, support for hidden rom area common flash memory interface (cfi) byte/word modes ? block erase architecture 8 8 kbytes/63 64 kbytes ? boot block architecture tc58fvm5t2a/3a: top boot block TC58FVM5B2A/3a: bottom boot block
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 2/63 ordering information tc58 f v m5 t2 a ft 65 speed version 65 = 65 ns package ft = tsop xb = fbga design rule a = 0.16 m function/boot block architecture/bank ratio t2 = page mode/top boot block/1:3:3:1 b2 = page mode/bottom boot block/1:3:3:1 t3 = page mode/top boot block/3:3:1:1 b3 = page mode/bottom boot block/1:1:3:3 capacity m5 = 32mbits supply voltage v = 3v system device type f = nor flash memory toshiba cmos e 2 prom ordering type boot block bank ratio package tc58fvm5t2aft65 top TC58FVM5B2Aft65 bottom 1:3:3:1 tc58fvm5t3aft65 top 3:3:1:1 tc58fvm5b3aft65 bottom 1:1:3:3 tsop i 48-p-1220-0.50 tc58fvm5t2axb65 top TC58FVM5B2Axb65 bottom 1:3:3:1 tc58fvm5t3axb65 top 3:3:1:1 tc58fvm5b3axb65 bottom 1:1:3:3 p-tfbga56-0710-0.80az
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 3/63 pin assignment (top view) tc58fvm5 ** aft pin names a-1, a0~a20 address input dq0~dq15 data input/output ce chip enable input oe output enable input byte word/byte select input we write enable input by / ry ready/busy output reset hardware reset input /acc wp write protect / program acceleration input nc not connected v dd power supply v ss ground pin assignment (top view) tc58fvm5 ** axb 1 2 3 4 5 6 7 8 a nc nc b nc nc c a3 a7 by / ry we a9 a13 d a4 a17 /acc wp reset a8 a12 e a2 a6 a18 nc a10 a14 f a1 a5 a20 a19 a11 a15 g a0 dq0 dq2 dq5 dq7 a16 h c dq8 dq10 dq12 dq14 byte j oe dq9 dq11 v dd dq13 dq15 k v ss dq1 dq3 dq4 dq6 v ss l nc nc m nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v ss a0 byte oe ce a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 nc a18 a17 a7 a6 a5 a4 a3 a2 a1 we reset /acc wp by / ry 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 4/63 block diagram by / ry buffer data latch control circuit command register i/o buffer address latch address buffer v dd v ss dq0 by / ry dq15 we byte reset ce oe a0 a20 a-1 /acc wp memory cell array bank3 memory cell array bank2 memory cell array bank0 memory cell array bank 1
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 5/63 mode selection byte mode word mode mode ce oe we a9 a6 a1 a0 reset /acc wp dq0~dq7 (1) dq0~dq15 read / page read l l h a9 a6 a1 a0 h * d out d out id read (manufacturer code) l l h v id l l l h * code code id read (device code) l l h v id l l h h * code code standby h * * * * * * h * high-z high-z output disable * h h * * * * * * high-z high-z write l h (2) a9 a6 a1 a0 h * d in d in block protect 1 l v id (2) v id l h l h * * * verify block protect l l h v id l h l h * code code temporary block unprotect * * * * * * * v id * * * hardware reset / standby * * * * * * * l * high-z high-z boot block protect * * * * * * * * l * * notes: * = v ih or v il , l = v il , h = v ih (1) dq8~dq14 are high-z and dq15/a-1 is address input in byte mode. addresses are a20~a0 in word mode ( byte = v ih ), a20~a-1 in byte mode ( byte = v il ). (2) pulse input id code table code type a20~a12 a6 a1 a0 code (hex) (1) manufacturer code * l l l 0098h tc58fvm5t2a * l l h 00c5h TC58FVM5B2A * l l h 0055h tc58fvm5t3a * l l h 00c6h device code tc58fvm5b3a * l l h 0056h verify block protect ba (2) l h l data (3) notes: * = v ih or v il , l = v il , h = v ih (1) dq8~dq14 are high-z and dq15/a-1 is address input in byte mode. (2) ba: block address (3) 0001h - protected block 0000h - unprotected block
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 6/63 command sequences first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle command sequence bus write cycles req?d addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h word 555h 2aah 555h read/reset byte 3 aaah aah 555h 55h aaah f0h ra (1) rd (2) word 555h 2aah bk (3) + 555h id read byte 3 aaah aah 555h 55h bk (3) + aaah 90h ia (4) id (5) word 555h 2aah 555h auto-program byte 4 aaah aah 555h 55h aaah a0h pa (6) pd (7) word 11 555h 2aah 555h auto pageprogram byte 19 aaah aah 555h 55h aaah e6h pa (6) pd (7) pa (6) pd (7) pa (6) pd (7) program suspend 1 bk (3) b0h program resume 1 bk (3) 30h word 555h 2aah 555h 555h 2aah 555h auto chip erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h word 555h 2aah 555h 555h 2aah auto block erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba (8) 30h block erase suspend 1 bk (3) b0h block erase resume 1 bk (3) 30h block protect 2 4 xxxh 60h bpa (9) 60h xxxh 40h bpa (9) bpd (10) word 555h 2aah bk (3) + 555h verify block protect byte 3 aaah aah 555h 55h bk (3) + aaah 90h bpa (9) bpd (10) word 555h 2aah 555h fast program set byte 3 aaah aah 555h 55h aaah 20h fast program 2 xxxh a0h pa (6) pd (7) fast program reset 2 xxxh 90h xxxh f0h (13) word 555h 2aah 555h hidden rom mode entry byte 3 aaah aah 555h 55h aaah 88h word 555h 2aah 555h hidden rom program byte 4 aaah aah 555h 55h aaah a0h pa (6) pd (7) word 555h 2aah 555h 555h 2aah hidden rom erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba (8) 30h word 555h 2aah 555h hidden rom mode exit byte 4 aaah aah 555h 55h aaah 90h xxxh 00h word bk (3) + 55h query command byte 2 bk (3) + aah 98h ca (11) cd (12) notes: the system should generate the following address patterns: word mode: 555h or 2aah on address pins a10~a0 dq8~dq15 are ignored in word mode. byte mode: aaah or 555h on address pins a10~a-1 (1) ra: read address (2) rd: read data (3) bk: bank address = a20~a18 (4) ia : bank address and id read address (a6, a1, a0) bank address = a20~a18 manufacturer code = (0, 0, 0) device code = (0, 0, 1) (5) id : id data (6) pa: program address ( input continuous 8 address from (a0,a1,a2)=(0,0,0) to (a0,a1,a2)=(1,1,1) in page program.) (7) pd: program data (8) ba: block address = a20~a12 (9) bpa: block address and id read address (a6, a1, a0) block address = a20~a12 id read address = (0, 1, 0) (10) bpd: verify data (11) ca: cfi address (12) cd: cfi data (13) f0h: 00h is valid too
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 7/63 simultaneous read/write operation the tc58fvm5t2a/b2a/t3a/b3a features a simultaneous read/write operation. the simultaneous read/write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. the tc58fvm5t2a/b2a/t3a/b3a has a total of four banks (4mbits : 12mbits : 12mbits : 4mbits ). banks can be switched between using the bank addresses (a20~a18). for a description of bank blocks and addresses, please refer to the block address table and block size table. the simultaneous read/write operation cannot perform multiple operations within a single bank. the table below shows the operation modes in which simultaneous operation can be performed. note that during auto-program execution or auto block erase operation, the simultaneous read/write operation cannot read data from addresses in the same bank which have not been selected for operation. data from these addresses can be read using the program suspend or erase suspend function, however. simultaneous read/write operation status of bank on which operation is being performed status of other banks read mode id read mode (1) auto-program mode auto-page program mode fast program mode (2) program suspend mode auto block erase mode auto multiple block erase mode (3) erase suspend mode program during erase suspend program suspend during erase suspend cfi mode read mode (1) only command mode is valid. (2) including times when acceleration mode is in use. (3) if the selected blocks are spread across all four banks, simultaneous operation cannot be carried out. operation modes in addition to the read, write and erase modes, the tc58fvm5t2a/b2a/t3a/b3a features many functions including block protection and data polling. when incorporating the device into a deign, please refer to the timing charts and flowcharts in combination with the description below. read mode ( page read ) to read data from the memory cell array, set the device to read mode. in read mode the device can perform high-speed random access and page read as asynchronous rom. the device is automatically set to read mode immediately after power-on or on completion of automatic operation. a software reset releases id read mode and the lock state which the device enters if automatic operation ends abnormally, and sets the device to read mode. a hardware reset terminates operation of the device and resets it to read mode. when reading data without changing the address immediately after power-on, either input a hardware reset or change ce from h to l.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 8/63 id read mode id read mode is used to read the device maker code and device code. the mode is useful in that it allows eprom programmers to identify the device type automatically. id read can be executed in two ways, as follows: (1) applying v id to a9 this method is used mainly by eprom programmers. applying v id to a9 sets the device to id read mode, outputting the maker code from address 00h and the device code from address 01h. releasing v id from a9 returns the device to read mode. with this method all banks are set to id read mode; thus, simultaneous operation cannot be performed. (2) input command sequence with this method simultaneous operation can be performed. inputting an id read command sets the specified bank to id read mode. banks are specified by inputting the bank address (bk) in the third bus write cycle of the command cycle. to read an id code, the bank address as well as the id read address must be specified. the maker code is output from address bk + 00; the device code is output from address bk + 01. from other banks data are output from the memory cells. inputting a reset command releases id read mode and returns the device to read mode. access time in id read mode is the same as that in read mode. for a list of the codes, please refer to the id code table. standby mode there are two ways to put the device into standby mode. (1) control using ce and reset with the device in read mode, input v dd 0.3 v to ce and reset . the device will enter standby mode and the current will be reduced to the standby current (i dds1 ). however, if the device is in the process of performing simultaneous operation, the device will not enter standby mode but will instead cause the operating current to flow. (2) control using reset only with the device in read mode, input v ss 0.3 v to reset . the device will enter standby mode and the current will be reduced to the standby current (i dds1 ). even if the device is in the process of performing simultaneous operation, this method will terminate the current operation and set the device to standby mode. this is a hardware reset and is described later. in standby mode dq is put in high-impedance state. auto-sleep mode this function suppresses power dissipation during reading. if the address input does not change for 150 ns, the device will automatically enter sleep mode and the current will be reduced to the standby current (i dds2 ). however, if the device is in the process of performing simultaneous operation, the device will not enter standby mode but will instead cause the operating current to flow. because the output data is latched, data is output in sleep mode. when the address is changed, sleep mode is automatically released, and data from the new address is output. output disable mode inputting v ih to oe disables output from the device and sets dq to high-impedance.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 9/63 command write the tc58fvm5t2a/b2a/t3a/b3a uses the standard jedec control commands for a single-power supply e 2 prom. a command write is executed by inputting the address and data into the command register. the command is written by inputting a pulse to we with ce = v il and oe = v ih ( we control). the command can also be written by inputting a pulse to ce with we = v il ( ce control). the address is latched on the falling edge of either we or ce . the data is latched on the rising edge of either we or ce . dq0~dq7 are valid for data input and dq8~dq15 are ignored. to abort input of the command sequence use the reset command. the device will reset the command register and enter read mode. if an undefined command is input, the command register will be reset and the device will enter read mode. software reset apply a software reset by inputting a read/reset command. a software reset returns the device from id read mode or cfi mode to read mode, releases the lock state if automatic operation has ended abnormally, and clears the command register. hardware reset a hardware reset initializes the device and sets it to read mode. when a pulse is input to reset for t rp , the device abandons the operation which is in progress and enters read mode after t ready . note that if a hardware reset is applied during data overwriting, such as a write or erase operation, data at the address or block being written to at the time of the reset will become undefined. after a hardware reset the device enters read mode if reset = v ih or standby mode if reset = v il . the dq pins are high-impedance when reset = v il . after the device has entered read mode, read operations and input of any command are allowed. comparison between software reset and hardware reset action software reset hardware reset releases id read mode or cfi mode. true true clears the command register. true true releases the lock state if automatic operation has ended abnormally. true true stops any automatic operation which is in progress. false true stops any operation other than the above and returns the device to read mode. false true /word mode byte is used select word mode (16 bits) or byte mode (8 bits) for the tc58fvm5t2a/b2a/t3a/b3a. if v ih is input to byte , the device will operate in word mode. read data or write commands using dq0~dq15. when v il is input to byte , read data or write commands using dq0~dq7. dq15/a-1 is used as the lowest address. dq8~dq14 will become high-impedance. byte
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 10/63 auto-program mode the tc58fvm5t2a/b2a/t3a/b3a can be programmed in either byte or word units. auto-program mode is set using the program command. the program address is latched on the falling edge of the we signal and data is latched on the rising edge of the fourth bus write cycle (with we control). auto programming starts on the rising edge of the we signal in the fourth bus write cycle. the program and program verify commands are automatically executed by the chip. the device status during programming is indicated by the hardware sequence flag. to read the hardware sequence flag, specify the address to which the write is being performed . during auto program execution, a command sequence for the bank on which execution is being performed cannot be accepted. to terminate execution, use a hardware reset. note that if the auto-program operation is terminated in this manner, the data written so far is invalid. any attempt to program a protected block is ignored. in this case the device enters read mode 3 s after the rising edge of the we signal in the fourth bus write cycle. if an auto-program operation fails, the device remains in the programming state and does not automatically return to read mode. the device status is indicated by the hardware sequence flag. either a reset command or a hardware reset is required to return the device to read mode after a failure. if a programming operation fails, the block which contains the address to which data could not be programmed should not be used. the device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. if this is attempted, execution of auto program will fail. this is a user error, not a device error. a cell containing 0 must be erased in order to set it to 1. auto-page program mode auto-page program is a function which enables to simultaneously program 8words or 16bytes data. in this mode program time for 32m bit is less than 60% compare with auto program mode. in word mode, input page program command during first bus write cycle to third bus write cycle. input program data and address of (a0,a1,a2)=(0,0,0) in forth bus write cycle. input increment address and program data during fifth bus write cycle to eleventh bus write cycle. after input eleventh bus write cycle , page program operation start. in byte mode, input increment address and program data of (a-1,a0,a1,a2)=(0,0,0,0)--- (a-1,a0,a1,a2)=(1,1,1,1) during fifth bus write cycle to nineteenth bus write cycle. fast program mode fast program is a function which enables execution of the command sequence for the auto program to be completed in two cycles. in this mode the first two cycles of the command sequence, which normally requires four cycles, are omitted. writing is performed in the remaining two cycles. to execute fast program, input the fast program command. write in this mode uses the fast program command but operation is the same at that for ordinary auto-program. the status of the device is indicated by the hardware sequence flag and read operations can be performed as usual. to exit this mode, the fast program reset command must be input. when the command is input, the device will return to read mode. acceleration mode the tc58fvm5t2a/b2a/t3a/b3a features acceleration mode which allows write time to be reduced. applying v acc to wp or acc automatically sets the device to acceleration mode. in acceleration mode, block protect mode changes to temporary block unprotect mode. write mode changes to fast program mode. modes are switched by the /acc wp signal; thus, there is no need for a temporary block unprotect operation or to set or reset fast program mode. operation of write is the same as in auto-program mode. removing v acc from /acc wp terminates acceleration mode.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 11/63 program suspend/resume mode program suspend is used to enable data read by suspending the write operation. the device accepts a program suspend command in write mode (including write operations performed during erase suspend) but ignores the command in other modes. when the command is input, the address of the bank on which write is being performed must be specified. after input of the command, the device will enter program suspend read mode after t susp . during program suspend, cell data read, id read and cfi data read can be performed. when data write is suspended, the address to which write was being performed becomes undefined. id read and cfi data read are the same as usual. after completion of program suspend input a program resume command to return to write mode. when inputting the command, specify the address of the bank on which write is being performed. if the id read or cfi data read functions is being used, abort the function before inputting the resume command. on receiving the resume command, the device returns to write mode and resumes outputting the hardware sequence flag for the bank to which data is being written. program suspend can be run in fast program mode or acceleration mode. however, note that when running program suspend in acceleration mode, v acc must not be released. auto chip erase mode the auto chip erase mode is set using the chip erase command. an auto chip erase operation starts on the rising edge of we in the sixth bus cycle. all memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. the device status is indicated by the hardware sequence flag. command input is ignored during an auto chip erase. a hardware reset can interrupt an auto chip erase operation. if an auto chip erase operation is interrupted, it cannot be completed correctly. hence an additional erase operation must be performed. any attempt to erase a protected block is ignored. if all blocks are protected, the auto erase operation will not be executed and the device will enter read mode 250 s after the rising edge of the we signal in the sixth bus cycle. if an auto chip erase operation fails, the device will remain in the erasing state and will not return to read mode. the device status is indicated by the hardware sequence flag. either a reset command or a hardware reset is required to return the device to read mode after a failure. in this case it cannot be ascertained which block the failure occurred in. either abandon use of the device altogether, or perform a block erase on each block, identify the failed block, and stop using it. the host processor must take measures to prevent subsequent use of the failed block.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 12/63 auto block erase / auto multi-block erase modes the auto block erase mode and auto multi-block erase mode are set using the block erase command. the block address is latched on the falling edge of the we signal in the sixth bus cycle. the block erase starts as soon as the erase hold time (t beh ) has elapsed after the rising edge of the we signal. when multiple blocks are erased, the sixth bus write cycle is repeated with each block address and auto block erase command being input within the erase hold time (this constitutes an auto multi-block erase operation). if a command other than an auto block erase command or erase suspend command is input during the erase hold time, the device will reset the command register and enter read mode. the erase hold time restarts on each successive rising edge of we . once operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. the device status is indicated by the setting of the hardware sequence flag. when the hardware sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specified. if the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out. all commands (except erase suspend) are ignored during an auto block erase or auto multi-block erase operation. either operation can be aborted using a hardware reset. if an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. any attempt to erase a protected block is ignored. if all the selected blocks are protected, the auto-erase operation is not executed and the device returns to read mode 250 s after the rising edge of the we signal in the last bus cycle. if an auto-erase operation fails, the device remains in erasing state and does not return to read mode. the device status is indicated by the hardware sequence flag. after a failure either a reset command or a hardware reset is required to return the device to read mode. if multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. in this case either abandon use of the device altogether, or perform a block erase on each block, identify the failed block, and stop using it. the host processor must take measures to prevent subsequent use of the failed block. erase suspend / erase resume modes erase suspend mode suspends auto block erase and reads data from or writes data to an unselected block. the erase suspend command is allowed during an auto block erase operation but is ignored in all other operation modes. when the command is input, the address of the bank on which erase is being performed must be specified. in erase suspend mode only a read, program or resume command can be accepted. if an erase suspend command is input during an auto block erase, the device will enter erase suspend read mode after t suse . the device status (erase suspend read mode) can be verified by checking the hardware sequence flag. if data is read consecutively from the block selected for auto block erase, the dq2 output will toggle and the dq6 output will stop toggling and by / ry will be set to high-impedance. inputting a write command during an erase suspend enables a write to be performed to a block which has not been selected for the auto block erase. data is written in the usual manner. to resume the auto block erase, input an erase resume command. on input of the command, the address of the bank on which the write was being performed must be specified. on receiving an erase resume command, the device returns to the state it was in when the erase suspend command was input. if an erase suspend command is input during the erase hold time, the device will return to the state it was in at the start of the erase hold time. at this time more blocks can be specified for erasing. if an erase resume command is input during an auto block erase, erase resumes. at this time toggle output of dq6 resumes and 0 is output on by / ry .
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 13/63 block protection block protection is a function for disabling writing and erasing specific blocks. block protection can be carried out in two ways: by supplying a high voltage (v id ) to the device (see block protection 1) or by supplying a high voltage and a command sequence (see block protection 2). (1) block protection 1 specify a device block address and make the following signal settings a9 = oe = v id , a1 = v ih and ce = a0 = a6 = v il . now when a pulse is input to we for t pplh , the device will start to write to the block protection circuit. block protection can be verified using the verify block protect command. inputting v il on oe sets the device to verify mode. 01h is output if the block is protected and 00h is output if the block is unprotected. if block protection was unsuccessful, the operation must be repeated. releasing v id from a9 and oe terminates this mode. (2) block protection 2 applying v id to reset and inputting the block protect 2 command also performs block protection. the first cycle of the command sequence is the set-up command. in the second cycle, the block protect command is input, in which a block address and a1 = v ih and a0 = a6 = v il are input. now the device writes to the block protection circuit. there is a wait of t pplh until this write is completed; however, no intervention is necessary during this time. in the third cycle the verify block protect command is input. this command verifies the write to the block protection circuit. read is performed in the fourth cycle. if the protection operation is complete, 01h is output. if a value other than 01h is output, block protection is not complete and the block protect command must be input again. removing the v id input from reset exits this mode. temporary block unprotection the tc58fvm5t2a/b2a/t3a/b3a has a temporary block unprotection feature which disables block protection for all protected blocks. unprotection is enabled by applying v id to the reset pin. now write and erase operations can be performed on all blocks except the boot blocks which have been protected by the boot block protect operation. the device returns to its previous state when v id is removed from the reset pin. that is, previously protected blocks will be protected again. verify block protect the verify block protect command is used to ascertain whether a block is protected or unprotected. verification is performed either by inputting the verify block protect command or by applying v id to the a9 pin, as for id read mode, and setting the block address = a0 = a6 = v il and a1 = v ih . if the block is protected, 01h is output. if the block is unprotected, 00h is output. boot block protection boot block protection temporarily protects certain boot blocks using a method different from ordinary block protection. neither v id nor a command sequence is required. protection is performed simply by inputting v il on /acc wp . the target blocks are the two pairs of boot blocks. the top boot blocks are ba69 and ba70; the bottom boot blocks are ba0 and ba1. inputting v ih on /acc wp releases the mode. from now on, if it is necessary to protect these blocks, the ordinary block protection mode must be used.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 14/63 hidden rom area the tc58fvm5t2a/b2a/t3a/b3a features a 64-kbyte hidden rom area which is separate from the memory cells. the area consists of one block. data read, write and protect can be performed on this block. because protect cannot be released, once the block is protected, data in the block cannot be overwritten. the hidden rom area is located in the address space indicated in the hidden rom area address table. to access the hidden rom area, input a hidden rom mode entry command. the device now enters hidden rom mode, allowing read, write, erase and block protect to be executed. write and erase operations are the same as auto operations except that the device is in hidden rom mode. however, regarding write operation, accelaration mode can not be performed during hidden rom mode. to protect the hidden rom area, use the block protection function. the operation of block protect here is the same as a normal block protect except that v ih rather than v id is input to reset . once the block has been protected, protection cannot be released, even using the temporary block unprotection function. use block protect carefully. note that in hidden rom mode, simultaneous operation cannot be performed for bank3 in top boot type and for bank0 in bottom boot type. to exit hidden rom mode, use the hidden rom mode exit command. this will return the device to read mode. hidden rom area address table byte mode word mode type boot block architecture address range size address range size tc58fvm5t2a tc58fvm5t3a top boot block 3f0000h~3fffffh 64 kbytes 1f8000h~1fffffh 32 kwords TC58FVM5B2A tc58fvm5b3a bottom boot block 000000h~00ffffh 64 kbytes 000000h~007fffh 32 kwords
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 15/63 common flash memory interface (cfi) the tc58fvm5t2a/b2a/t3a/b3a conforms to the cfi specifications. to read information from the device, input the query command followed by the address. in word mode dq8~dq15 all output 0s. to exit this mode, input the reset command. cfi code table address a6~a0 data dq15~dq0 description 10h 11h 12h 0051h 0052h 0059h ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 2: amd/fj standard type 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set 0: none exists 19h 1ah 0000h 0000h address for alternate oem extended table 1bh 0023h v dd (min) (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1ch 0036h v dd (max) (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1dh 0000h v pp (min) voltage 1eh 0000h v pp (max) voltage 1fh 0004h typical time-out per single byte/word write (2 n s) 20h 0000h typical time-out for minimum size buffer write (2 n s) 21h 000ah typical time-out per individual block erase (2 n ms) 22h 0000h typical time-out for full chip erase (2 n ms) 23h 0005h maximum time-out for byte/word write (2 n times typical) 24h 0000h maximum time-out for buffer write (2 n times typical) 25h 0004h maximum time-out per individual block erase (2 n times typical) 26h 0000h maximum time-out for full chip erase (2 n times typical) 27h 0016h device size (2 n byte) 28h 29h 0002h 0000h flash device interface description 2: 8/ 16 2ah 2bh 0004h 0000h maximum number of bytes in multi-byte write (2 n )
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 16/63 address a6~a0 data dq15~dq0 description 2ch 0002h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information bits 0~15: y = block number bits 16~31: z = block size (z 256 bytes) 31h 32h 33h 34h 003eh 0000h 0000h 0001h erase block region 2 information 40h 41h 42h 0050h 0052h 0049h ascii string ?pri? 43h 0031h major version number, ascii 44h 0031h minor version number, ascii 45h 0000h address-sensitive unlock 0: required 1: not required 46h 0002h erase suspend 0: not supported 1: for read-only 2: for read & write 47h 0001h block protect 0: not supported x: number of blocks per group 48h 0001h block temporary unprotect 0: not supported 1: supported 49h 0004h block protect/unprotect scheme 4ah 0001h simultaneous operation 0: not supported 1: supported 4bh 0000h burst mode 0: not supported 4ch 0001h page mode 0: not supported 1: supported 4dh 0085h v acc (min) voltage dq7~dq4: 1 v dq3~dq0: 100 mv 4eh 0095h v acc (max) voltage dq7~dq4: 1 v dq3~dq0: 100 mv 4fh 000xh top/bottom boot block flag 2: TC58FVM5B2A 3: tc58fvm5t2a 50h 0001h program suspend 0: not supported 1: supported
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 17/63 address a6~a0 data dq15~dq0 description 57h 0004h bank organization 00h : data at 4ah is zero x: number of banks 58h 00xxh bank0 region information x = number of blocks in bank0 tc58fvm5t2a : 08h TC58FVM5B2A: 0fh tc58fvm5t3a : 18h tc58fvm5b3a: 0fh 59h 00xxh bank1 region information x = number of blocks in bank1 tc58fvm5t2a : 18h TC58FVM5B2A: 18h tc58fvm5t3a : 18h tc58fvm5b3a: 08h 5ah 00xxh bank2 region information x = number of blocks in bank2 tc58fvm5t2a : 18h TC58FVM5B2A: 18h tc58fvm5t3a : 08h tc58fvm5b3a: 18h 5bh 00xxh bank3 region information x = number of blocks in bank3 tc58fvm5t2a : 0fh TC58FVM5B2A: 08h tc58fvm5t3a : 0fh tc58fvm5b3a: 18h
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 18/63 hardware sequence flags the tc58fvm5t2a/b2a/t3a/b3a has a hardware sequence flag which allows the device status to be determined during an auto mode operation. the output data is read out using the same timing as that used when ce = oe = v il in read mode. the by / ry output can be either high or low. the device re-enters read mode automatically after an auto mode operation has been completed successfully. the hardware sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. status dq7 dq6 dq5 dq3 dq2 by / ry auto programming / auto page programming 7 dq (4) toggle 0 0 1 0 read in program suspend (1) data data data data data high-z selected (2) 0 toggle 0 0 toggle 0 erase hold time not-selected (3) 0 toggle 0 0 1 0 selected 0 toggle 0 1 toggle 0 in auto erase auto erase not-selected 0 toggle 0 1 1 0 selected 1 1 0 0 toggle high-z read not-selected data data data data data high-z selected 7 dq (4) toggle 0 0 toggle 0 in progress in erase suspend programming not-selected 7 dq (4) toggle 0 0 1 0 auto programming / auto page programming 7 dq (4) toggle 1 0 1 0 auto erase 0 toggle 1 1 na 0 time limit exceeded programming in erase suspend 7 dq (4) toggle 1 0 na 0 notes:dq outputs cell data and by / ry goes high-impedence when the operation has been completed. dq0 and dq1 pins are reserved for future use. 0 is output on dq0, dq1 and dq4. (1) data output from an address to which write is being performed is undefined. (2) output when the block address selected for auto block erase is specified and data is read from there. during auto chip erase, all blocks are selected. (3) output when a block address not selected for auto block erase of same bank as selected block is specified and data is read from there. (4) in case of page program operation is program data of (a0,a1,a2)=(1,1,1) in eleventh bus write cycle in word mode. program data of (a-1,a0,a1,a2)=(1,1,1,1) in nineteenth bus write cycle in byte mode. dq7 ( polling) during an auto-program or auto-erase operation, the device status can be determined using the data polling function. data polling begins on the rising edge of we in the last bus cycle. in an auto-program operation, dq7 outputs inverted data during the programming operation and outputs actual data after programming has finished. in an auto-erase operation, dq7 outputs 0 during the erase operation and outputs 1 when the erase operation has finished. if an auto-program or auto-erase operation fails, dq7 simply outputs the data. when the operation has finished, the address latch is reset. data polling is asynchronous with the oe signal. data
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 19/63 dq6 (toggle bit 1) the device status can be determined by the toggle bit function during an auto-program or auto-erase operation. the toggle bit begins toggling on the rising edge of we in the last bus cycle. dq6 alternately outputs a 0 or a 1 for each oe access while ce = v il while the device is busy. when the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. if the operation fails, the dq6 output toggles. if an attempt is made to execute an auto program operation on a protected block, dq6 will toggle for around 3 s. it will then stop toggling. if an attempt is made to execute an auto erase operation on a protected block, dq6 will toggle for around 250 s. it will then stop toggling. after toggling has stopped the device will return to read mode. dq5 (internal time-out) if the internal timer times out during a program or erase operation, dq5 outputs a 1. this indicates that the operation has not been completed within the allotted time. any attempt to program a 1 into a cell containing a 0 will fail (see auto-program mode). in this case dq5 outputs a 1. either a hardware reset or a software reset command is required to return the device to read mode. dq3 (block erase timer) the block erase operation starts 50 s (the erase hold time) after the rising edge of we in the last command cycle. dq3 outputs a 0 for the duration of the block erase hold time and a 1 when the block erase operation starts. additional block erase commands can only be accepted during the block erase hold time. each block erase command input within the hold time resets the timer, allowing additional blocks to be marked for erasing. dq3 outputs a 1 if the program or erase operation fails. dq2 (toggle bit 2) dq2 is used to indicate which blocks have been selected for auto block erase or to indicate whether the device is in erase suspend mode. if data is read continuously from the selected block during an auto block erase, the dq2 output will toggle. now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. if data is read continuously from the block selected for auto block erase while the device is in erase suspend mode, the dq2 output will toggle. because the dq6 output is not toggling, it can be determined that the device is in erase suspend mode. if data is read from the address to which data is being written during erase suspend in programming mode, dq2 will output a 1. (ready/ ) tc58fvm5t2a/b2a/t3a/b3a has a by / ry signal to indicate the device status to the host processor. a 0 (busy state) indicates that an auto-program or auto-erase operation is in progress. a 1 (ready state) indicates that the operation has finished and that the device can now accept a new command. by / ry outputs a 0 when an operation has failed. by / ry outputs a 0 after the rising edge of we in the last command cycle. during an auto block erase operation, commands other than erase suspend are ignored. by / ry outputs a 1 during an erase suspend operation. the output buffer for the by / ry pin is an open-drain type circuit, allowing a wired-or connection. a pull-up resistor must be inserted between v dd and the by / ry pin. by / ry busy
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 20/63 data protection the tc58fvm5t2a/b2a/t3a/b3a includes a function which guards against malfunction or data corruption. protection against program/erase caused by low supply voltage to prevent malfunction at power-on or power-down, the device will not accept commands while v dd is below v lko . in this state, command input is ignored. if v dd drops below v lko during an auto operation, the device will terminate auto-program execution. in this case, auto operation is not executed again when v dd return to recommended v dd voltage therefore, command need to be input to execute auto operation again. when v dd > v lko , make up countermeasure to be input accurately command in system side please. protection against malfunction caused by glitches to prevent malfunction during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns (typ.) input on we , ce or oe . however, if a glitch exceeding 3 ns (typ.) occurs and the glitch is input to the device malfunction may occur. the device uses standard jedec commands. it is conceivable that, in extreme cases, system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it. then, even if a proper command is input, the device may not operate. to avoid this possibility, clear the command register before command input. in an environment prone to system noise, toshiba recommend input of a software or hardware reset before command input. protection against malfunction at power-on to prevent damage to data caused by sudden noise at power-on, when power is turned on with we = ce = v il the device does not latch the command on the first rising edge of we or ce . instead, the device automatically resets the command register and enters read mode.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 21/63 absolute maximum ratings symbol parameter range unit v dd v dd supply voltage ? 0.6~4.6 v v in input voltage ? 0.6~v dd + 0.5 ( 4.6) v v dq input/output voltage ? 0.6~v dd + 0.5 ( 4.6) v v idh maximum input voltage for a9, oe and reset 13.0 v v acch maximum input voltage for /acc wp 10.5 v p d power dissipation 126 mw t solder soldering temperature (10s) 260 c t stg storage temperature ? 55~150 c t opr operating temperature ? 40~85 c i oshort output short-circuit current (1) 100 ma (1) outputs should be shorted for no more than one second. no more than one output should be shorted at a time. capacitance (ta = = = = 25c, f = = = = 1 mhz) tsopi symbol parameter condition max unit c in input pin capacitance v in = 0 v tbd pf c out output pin capacitance v out = 0 v tbd pf c in2 control pin capacitance v in = 0 v tbd pf this parameter is periodically sampled and is not tested for every device. tfbga symbol parameter condition max unit c in input pin capacitance v in = 0 v tbd pf c out output pin capacitance v out = 0 v tbd pf c in2 control pin capacitance v in = 0 v tbd pf this parameter is periodically sampled and is not tested for every device. recommended dc operating conditions symbol parameter min max unit v dd v dd supply voltage 2.3 3.6 v ih input high-level voltage 0.7 v dd v dd + 0.3 (2) v il input low-level voltage ? 0.3 (1) 0.2 v dd v id high-level voltage for a9, oe and reset (3) 11.4 12.6 v acc high-level voltage for /acc wp (3) 8.5 9.5 v ta operating temperature ? 40 85 c (1) ? 2 v (pulse width of 20 ns max) (2) + 2 v (pulse width of 20 ns max) (3) do not apply v id /v acc when the supply voltage is not within the device's recommended operating voltage range.
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 22/63 dc characteristics symbol parameter condition min typ. max unit i li input leakage current 0 v v in v dd ? ? 1 i lo output leakage current 0 v v out v dd ? ? 1 a i oh = ? 0.1 ma v dd ? 0.4 ? ? v oh output high voltage i oh = ? 2.5 ma 0.85 v dd ? ? v ol output low voltage i ol = 4.0 ma ? ? 0.4 v i ddo1 v dd average random read current v in = v ih /v il , i out = 0 ma t cycle = t rc = 100 ns(min) ? 35 55 i ddo2 v dd average program current v in = v ih /v il , i out = 0 ma ? 8 15 i ddo3 v dd average erase current v in = v ih /v il , i out = 0 ma ? 8 15 i ddo4 v dd average read-while-program current v in = v ih /v il , i out = 0 ma t cycle = t rc = 100 ns(min) ? 43 70 i ddo5 v dd average read-while-erase current v in = v ih /v il , i out = 0 ma t cycle = t rc = 100 ns(min) ? 43 70 i ddo6 v dd average program-while- erase-suspend current v in = v ih /v il , i out = 0 ma ? 8 15 i ddo7 v dd average page read current v in = v ih /v il , i out = 0 ma ? 1 5 i ddo8 v dd average address increment read current (2) v in = v ih /v il , i out = 0 ma t rc = 100 ns(min) t prc = 25ns(min) ? 5 11 ma i dds1 v dd standby current ce = reset = v dd or reset = v ss ? 2 10 i dds2 v dd standby current (automatic sleep mode (1) ) v ih = v dd v il = v ss ? 2 10 i id high-voltage input current for a9, oe and reset 11.4 v v id 12.6 v ? ? 35 a i acc high-voltage input current for /acc wp 8.5 v v acc 9.5 v ? ? 20 ma v lko low-v dd lock-out voltage ? 1.5 ? 2.0 v (1) the device enters automatic sleep mode in which the address remains fixed for during 150 ns. (2) (i ddo1 +i ddo7 x7) 8words ac test conditions parameter condition input pulse level v dd , 0.0 v input pulse rise and fall time (10%~90%) 5 ns timing measurement reference level (input) vdd/2 , vdd/2 timing measurement reference level (output) vdd/2 , vdd/2 output load c l (100 pf) + 1 ttl gate / c l (30 pf) + 1 ttl gate
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 23/63 ac characteristics and operating conditions read cycle product name tc58fvm5t2a/b2a/t3a/b3a vdd voltage (v) vdd=2.7-3.6v vdd=2.3-3.6v output load capacitance (cl) 30 pf 100 pf 30 pf 100 pf symbol parameter min max min max min max min max unit t rc read cycle time 65 ? 70 ? 70 ? 75 ? ns t prc page read cycle time 25 ? 30 ? 30 ? 35 ? ns t acc address access time ? 65 ? 70 ? 70 ? 75 ns t ce ce access time ? 65 ? 70 ? 70 ? 75 ns t oe oe access time ? 25 ? 30 ? 30 ? 35 ns t pacc page access time ? 25 ? 30 ? 30 ? 35 ns t cee ce to output low-z 0 ? 0 ? 0 ? 0 ? ns t oee oe to output low-z 0 ? 0 ? 0 ? 0 ? ns t oh output data hold time 0 ? 0 ? 0 ? 0 ? ns t df1 ce to output high-z ? 25 ? 25 ? 25 ? 25 ns t df2 oe to output high-z ? 25 ? 25 ? 25 ? 25 ns block protect symbol parameter min max unit t vpt v id transition time 4 ? s t vps v id set-up time 4 ? s t cesp ce set-up time 4 ? s t vph oe hold time 4 ? s t pplh we low-level hold time 100 ? s program and erase characteristics symbol parameter min typ. max unit auto-program time (byte mode) ? 8 300 s t ppw auto-program time (word mode) ? 11 300 s t ppaw auto-page program time ? 45 2400 s t pcew auto chip erase time ? 50 710 s t pbew auto block erase time ? 0.7 10 s t ew erase/program cycle 10 5 ? ? cycles * auto chip erase time and auto block erase time include internal pre program time .
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 24/63 command write/program/erase cycle symbol parameter min max unit t cmd command write cycle time 60 ? ns tas address set-up time / byte set-up time 0 ? ns t ah address hold time / byte hold time 30 ? ns t ds data set-up time 30 ? ns t dh data hold time 0 ? ns t welh we low-level hold time ( we control ) 30 ? ns t wehh we high-level hold time ( we control ) 20 ? ns t ces ce set-up time to we active ( we control) 0 ? ns t ceh ce hold time from we high level ( we control) 0 ? ns t celh ce low-level hold time ( ce control) 30 ? ns t cehh ce high-level hold time ( ce control) 20 ? ns t wes we set-up time to ce active ( ce control) 0 ? ns t weh we hold time from ce high level ( ce control) 0 ? ns t oes oe set-up time 0 ? ns t oehp oe hold time (toggle, data polling) 10 ? ns t oeht oe high-level hold time (toggle) 20 ? ns t aht address hold time (toggle) 0 ? ns t ast address set-up time (toggle) 0 ? ns t beh erase hold time 50 ? s t vds v dd set-up time 500 ? s program/erase valid to by / ry delay ? 90 ns t busy program/erase valid to by / ry delay during suspend mode ? 300 ns t rp reset low-level hold time 500 ? ns t ready reset low-level to read mode ? 20 s t rb by / ry recovery time 0 ? ns t rh reset recovery time 50 ? ns t cebts ce set-up time byte transition 5 ? ns t btd byte to output high-z ? 30 ns t susp program suspend command to suspend mode ? 1.6 s t suspa page program suspend command to suspend mode ? 2.0 s t resp program resume command to program mode ? 1 s t suse erase suspend command to suspend mode ? 15 s t rese erase resume command to erase mode ? 1 s
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 25/63 timing diagrams read / id read operation id read operation (apply v id to a9) page read operation v ih or v il data invalid a0 a1 t rc t acc a6 ce t vps t ce t oe a9 oe v id v ih we d out manufacturer code device code hi-z hi-z hi-z read mode id read mode read mode address t rc we t df2 t cee t oeh ce t ce t acc t oh d out output data valid hi-z oe t oee t oe t df1 hi-z
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 26/63 read after command input ( only hidden rom / cfi read) address(a3-20))) address(0-2) t acc ce oe we d out hi-z hi-z t pacc d out d out d out d out d out d out d out t ce t oe d out t rc t prc address we ce d out d out valid hi-z oe hi-z last command address command data t wehh +t acc
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 27/63 command write operation this is the timing of the command write operation. the timing which is described in the following pages is essentially the same as the timing shown on this page. ? we control ? ce control address ce d in command address t as t cmd t ces t wel we t ceh t ah t dh t ds t wehh command data address d in command address t as t cmd t wes t weh we t ah t dh t ds t celh ce t cehh command data
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 28/63 id read operation (input command sequence) address we ce d in t cmd d out bk + 00h bk + 555h 2aah 555h t rc 55h 90h t oes note: word mode address shown. bk: bank address oe bk + 01h aah manufacturer code device code hi-z read mode (input of id read command sequence) id read mode address we ce d in t cmd d out 555h 2aah 555h 55h oe aah f0h id read mode (input of reset command sequence) read mode (continued) hi-z
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 29/63 auto-program operation ( control) we address ce we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vds note: word mode address shown. pa: program address pd: program data v dd oe pa hi-z aah 55h a0h pd
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 30/63 auto page program operation ( control) t cmd d out t vds note: word mode address shown. pa: program address pd: program data v dd d out 7 dq hi-z address(a0-2) 0h 1h 2h 3h 4h 5h 7h 6h t oehp t ppaw oe ce t oes e6h d in aah 55h pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 we address(a3-20) pa pa 7h 555h 2aah 555h we
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 31/63 auto chip erase / auto block erase operation ( control) auto-program operation ( control) ce we note: word mode address shown. ba: block address for auto block erase operation ce oe we v dd address d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vds 555h 2aah 555h 555h 2aah 555h/ba address we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vds note: word mode address shown. pa: program address pd: program data v dd oe pa hi-z aah 55h a0h pd ce
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 32/63 auto page program operation ( control) t cmd d out t vds note: word mode address shown. pa: program address pd: program data v dd d out 7 dq hi-z address(a0-2) 0h 1h 2h 3h 4h 5h 7h 6h t oehp t ppaw oe ce t oes e6h d in aah 55h pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 we address(a3-20) pa pa 7h 555h 2aah 555h ce
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 33/63 auto chip erase / auto block erase operation ( control) ce oe we v dd address 555h d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vds 555h/ba 2aah 555h 555h 2aah note: word mode address shown. ba: block address for auto block erase operation ce
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 34/63 program/erase suspend operation program/erase resume operation address ce we d in d out b0h d out ra: read address oe hi-z by / ry t ce t oe t susp /t suse suspend mode program/erase mode hi-z ra bk address ce we d in d out pa: program address bk: bank address ba: block address ra: read address flag: hardware sequence flag oe hi-z by / ry 30h program/erase mode suspend mode hi-z ra pa/ba t oes t resp /t rese t df1 d out t df2 flag t ce t oe bk
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 35/63 during auto program/erase operation hardware reset operation read after command input sequence during operation ce we by / ry t busy reset by / ry we by / ry t rp t ready t rb reset address reset d out t rc t rh t acc output data valid t oh hi-z
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 36/63 during read operation during write operation byte byte ce byte t cebts oe t btd dq0~dq7 t acc dq15/a-1 data output data output data output data output address input dq8~dq14 ce byte t as we t ah
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 37/63 hardware sequence flag ( polling) hardware sequence flag (toggle bit) data address ce t cmd last command address t df1 t df2 pa/ba d in t ppw /t pcew /t pbew t oh last command data we t oehp t ce t oe dq0~dq6 invalid dq7 7 dq oe pa: program address ba: block address t busy by / ry valid valid t acc valid valid address ce oe d in we t oe t oehp t oeht dq2/6 stop * toggle valid toggle toggle * dq2/dq6 stops toggling when auto operation has been completed. t busy by / ry t ce last command data toggle t aht t aht t ast t ast
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 38/63 block protect 1 operation address a0 block protect a6 a1 ba t vpt a9 v id v ih verify block protect ce oe we ba: block address * : 01h indicates that block is protected. d out hi-z t vps v id v ih t cesp t pplh 01h * t oe hi-z t vph t vph
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 39/63 block protect 2 operation address a0 a6 ce t cmd oe ba ba t oe ba: block address ba + 1: address of next block * : 01h indicates that block is protected. we a1 ba + 1 t cmd t cmd t rc t pplh 60h 40h 60h 60h 01h * d in d out hi-z v ih v id t vps reset ba
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 40/63 flowcharts auto-program address = address + 1 no yes auto-program command sequence (see below) data polling or toggle bit last address? start 555h/aah 2aah/55h program address/ program data 555h/a0h auto-program command sequence (address/data) note: the above command sequence takes place in word mode. auto-program completed
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 41/63 auto-page program 555h/aah 2aah/55h 555h/e6h program address (a2=0,a1=0,a0=0) / program data program address (a2=0,a1=0,a0=1) / program data program address (a2=0,a1=1,a0=0) / program data program address (a2=0,a1=1,a0=1) / program data program address (a2=1,a1=1,a0=1) / program data program address (a2=1,a1=1,a0=0) / program data program address (a2=1,a1=0,a0=1) / program data program address (a2=1,a1=0,a0=0) / program data address = address + 1 no yes data polling or toggle bit last address ? start auto page program command sequence ( see below ) ` auto-program completed
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 42/63 fast program address = address + 1 no yes fast program command sequence (see below) data polling or toggle bit last address? start xxxh/a0h program address/ program data fast program command sequence (address/data) fast program completed fast program set command sequence (see below) program sequence (see below) 555h/aah 2aah/55h 555h/20h fast program set command sequence (address/data) xxxh/90h xxxh/f0h fast program reset command sequence (address/data)
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 43/63 auto erase auto erase command sequence (see below) data polling or toggle bit start 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h block address/30h block address/30h block address/30h auto chip erase command sequence (address/data) auto block / auto multi-block erase command sequence (address/data) additional address inputs during a uto multi-block erase note: the above command sequence takes place in word mode. auto erase completed
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 44/63 dq7 polling dq6 toggle bit data yes no yes no read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq7 = data? dq5 = 1? dq7 = data? no yes 1) 1) : dq7 must be rechecked even if dq5 = 1 because dq7 may change at the same time as dq5. fail pass va: byte address for programming any of the addresses within the block being erased during a block erase operation ?don?t care? during a chip erase operation any address not within the current block during an erase suspend operation no no no yes read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq6 = toggle? dq5 = 1? dq6 = toggle? yes yes 1) 1) : dq6 must be rechecked even if dq5 = 1 because dq6 may stop toggling at the same time that dq5 changes to 1. fail pass
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 45/63 block protect 1 yes no plscnt = 1 we = v il start plscnt = 25? protect another block? data = 01h? plscnt = plscnt + 1 set up block address addr. = bpa oe = a9 = v id , ce = v il wait for 100 s verify block protect remove v id from a9 yes no oe = v il no yes bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) wait for 4 s wait for 4 s we = v ih wait for 4 s block protect complete device failed oe = v ih wait for 4 s
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 46/63 block protect 2 bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) no no block protect 2 command first bus write cycle (xxxh/60h) verify block protect start plscnt = 25? protect another block? wait for 100 s remove v id from reset yes no yes set up address addr. = bpa plscnt = 1 remove v id from reset plscnt = plscnt + 1 wait for 4 s reset = v id block protect 2 command second bus write cycle (bpa/60h) block protect 2 command third bus write cycle (xxxh/40h) yes data = 01h? reset command block protect complete reset command device failed
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 47/63 block address tables (1) tc58fvm5t2a (top boot block) block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba0 l l l l l l * * * 000000h~00ffffh 000000h~007fffh ba1 l l l l l h * * * 010000h~01ffffh 008000h~00ffffh ba2 l l l l h l * * * 020000h~02ffffh 010000h~017fffh ba3 l l l l h h * * * 030000h~03ffffh 018000h~01ffffh ba4 l l l h l l * * * 040000h~04ffffh 020000h~027fffh ba5 l l l h l h * * * 050000h~05ffffh 028000h~02ffffh ba6 l l l h h l * * * 060000h~06ffffh 030000h~037fffh bk0 ba7 l l l h h h * * * 070000h~07ffffh 038000h~03ffffh ba8 l l h l l l * * * 080000h~08ffffh 040000h~047fffh ba9 l l h l l h * * * 090000h~09ffffh 048000h~04ffffh ba10 l l h l h l * * * 0a0000h~0affffh 050000h~057fffh ba11 l l h l h h * * * 0b0000h~0bffffh 058000h~05ffffh ba12 l l h h l l * * * 0c0000h~0cffffh 060000h~067fffh ba13 l l h h l h * * * 0d0000h~0dffffh 068000h~06ffffh ba14 l l h h h l * * * 0e0000h~0effffh 070000h~077fffh ba15 l l h h h h * * * 0f0000h~0fffffh 078000h~07ffffh ba16 l h l l l l * * * 100000h~10ffffh 080000h~087fffh ba17 l h l l l h * * * 110000h~11ffffh 088000h~08ffffh ba18 l h l l h l * * * 120000h~12ffffh 090000h~097fffh ba19 l h l l h h * * * 130000h~13ffffh 098000h~09ffffh ba20 l h l h l l * * * 140000h~14ffffh 0a0000h~0a7fffh ba21 l h l h l h * * * 150000h~15ffffh 0a8000h~0affffh ba22 l h l h h l * * * 160000h~16ffffh 0b0000h~0b7fffh ba23 l h l h h h * * * 170000h~17ffffh 0b8000h~0bffffh ba24 l h h l l l * * * 180000h~18ffffh 0c0000h~0c7fffh ba25 l h h l l h * * * 190000h~19ffffh 0c8000h~0cffffh ba26 l h h l h l * * * 1a0000h~1affffh 0d0000h~0d7fffh ba27 l h h l h h * * * 1b0000h~1bffffh 0d8000h~0dffffh ba28 l h h h l l * * * 1c0000h~1cffffh 0e0000h~0e7fffh ba29 l h h h l h * * * 1d0000h~1dffffh 0e8000h~0effffh ba30 l h h h h l * * * 1e0000h~1effffh 0f0000h~0f7fffh bk1 ba31 l h h h h h * * * 1f0000h~1fffffh 0f8000h~0fffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 48/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba32 h l l l l l * * * 200000h~20ffffh 100000h~107fffh ba33 h l l l l h * * * 210000h~21ffffh 108000h~10ffffh ba34 h l l l h l * * * 220000h~22ffffh 110000h~117fffh ba35 h l l l h h * * * 230000h~23ffffh 118000h~11ffffh ba36 h l l h l l * * * 240000h~24ffffh 120000h~127fffh ba37 h l l h l h * * * 250000h~25ffffh 128000h~12ffffh ba38 h l l h h l * * * 260000h~26ffffh 130000h~137fffh ba39 h l l h h h * * * 270000h~27ffffh 138000h~13ffffh ba40 h l h l l l * * * 280000h~28ffffh 140000h~147fffh ba41 h l h l l h * * * 290000h~29ffffh 148000h~14ffffh ba42 h l h l h l * * * 2a0000h~2affffh 150000h~157fffh ba43 h l h l h h * * * 2b0000h~2bffffh 158000h~15ffffh ba44 h l h h l l * * * 2c0000h~2cffffh 160000h~167fffh ba45 h l h h l h * * * 2d0000h~2dffffh 168000h~16ffffh ba46 h l h h h l * * * 2e0000h~2effffh 170000h~177fffh ba47 h l h h h h * * * 2f0000h~2fffffh 178000h~17ffffh ba48 h h l l l l * * * 300000h~30ffffh 180000h~187fffh ba49 h h l l l h * * * 310000h~31ffffh 188000h~18ffffh ba50 h h l l h l * * * 320000h~32ffffh 190000h~197fffh ba51 h h l l h h * * * 330000h~33ffffh 198000h~19ffffh ba52 h h l h l l * * * 340000h~34ffffh 1a0000h~1a7fffh ba53 h h l h l h * * * 350000h~35ffffh 1a8000h~1affffh ba54 h h l h h l * * * 360000h~36ffffh 1b0000h~1b7fffh bk2 ba55 h h l h h h * * * 370000h~37ffffh 1b8000h~1bffffh ba56 h h h l l l * * * 380000h~38ffffh 1c0000h~1c7fffh ba57 h h h l l h * * * 390000h~39ffffh 1c8000h~1cffffh ba58 h h h l h l * * * 3a0000h~3affffh 1d0000h~1d7fffh ba59 h h h l h h * * * 3b0000h~3bffffh 1d8000h~1dffffh ba60 h h h h l l * * * 3c0000h~3cffffh 1e0000h~1e7fffh ba61 h h h h l h * * * 3d0000h~3dffffh 1e8000h~1effffh bk3 ba62 h h h h h l * * * 3e0000h~3effffh 1f0000h~1f7fffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 49/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba63 h h h h l l l 3f0000h~3f1fffh 1f8000h~1f8fffh ba64 h h h h l l 3f2000h~3f3fffh 1f9000h~1f9fffh ba65 h h h h h h l h l 3f4000h~3f5fffh 1fa000h~1fafffh ba66 h h h h h h l h h 3f6000h~3f7fffh 1fb000h~1fbfffh ba67 h h h h h h h l l 3f8000h~3f9fffh 1fc000h~1fcfffh ba68 h h h h h h h l h 3fa000h~3fbfffh 1fd000h~1fdfffh ba69 h h h h h h h h l 3fc000h~3fdfffh 1fe000h~1fefffh bk3 ba70 h h h h h h h h h 3fe000h~3fffffh 1ff000h~1fffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 50/63 (2) TC58FVM5B2A (bottom boot block) block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba0 l l l l l l l l l 000000h~001fffh 000000h~000fffh ba1 l l l l l l l l h 002000h~003fffh 001000h~001fffh ba2 l l l l l l l h l 004000h~005fffh 002000h~002fffh ba3 l l l l l l l h h 006000h~007fffh 003000h~003fffh ba4 l l l l l l h l l 008000h~009fffh 004000h~004fffh ba5 l l l l l l h l h 00a000h~00bfffh 005000h~005fffh ba6 l l l l l l h h l 00c000h~00dfffh 006000h~006fffh ba7 l l l l l l h h h 00e000h~00ffffh 007000h~007fffh ba8 l l l l l h * * * 010000h~01ffffh 008000h~00ffffh ba9 l l l l h l * * * 020000h~02ffffh 010000h~017fffh ba10 l l l l h h * * * 030000h~03ffffh 018000h~01ffffh ba11 l l l h l l * * * 040000h~04ffffh 020000h~027fffh ba12 l l l h l h * * * 050000h~05ffffh 028000h~02ffffh ba13 l l l h h l * * * 060000h~06ffffh 030000h~037fffh bk0 ba14 l l l h h h * * * 070000h~07ffffh 038000h~03ffffh ba15 l l h l l l * * * 080000h~08ffffh 040000h~047fffh ba16 l l h l l h * * * 090000h~09ffffh 048000h~04ffffh ba17 l l h l h l * * * 0a0000h~0affffh 050000h~057fffh ba18 l l h l h h * * * 0b0000h~0bffffh 058000h~05ffffh ba19 l l h h l l * * * 0c0000h~0cffffh 060000h~067fffh ba20 l l h h l h * * * 0d0000h~0dffffh 068000h~06ffffh ba21 l l h h h l * * * 0e0000h~0effffh 070000h~077fffh ba22 l l h h h h * * * 0f0000h~0fffffh 078000h~07ffffh ba23 l h l l l l * * * 100000h~10ffffh 080000h~087fffh ba24 l h l l l h * * * 110000h~11ffffh 088000h~08ffffh ba25 l h l l h l * * * 120000h~12ffffh 090000h~097fffh ba26 l h l l h h * * * 130000h~13ffffh 098000h~09ffffh ba27 l h l h l l * * * 140000h~14ffffh 0a0000h~0a7fffh ba28 l h l h l h * * * 150000h~15ffffh 0a8000h~0affffh ba29 l h l h h l * * * 160000h~16ffffh 0b0000h~0b7fffh bk1 ba30 l h l h h h * * * 170000h~17ffffh 0b8000h~0bffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 51/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba31 l h h l l l * * * 180000h~18ffffh 0c0000h~0c7fffh ba32 l h h l l h * * * 190000h~19ffffh 0c8000h~0cffffh ba33 l h h l h l * * * 1a0000h~1affffh 0d0000h~0d7fffh ba34 l h h l h h * * * 1b0000h~1bffffh 0d8000h~0dffffh ba35 l h h h l l * * * 1c0000h~1cffffh 0e0000h~0e7fffh ba36 l h h h l h * * * 1d0000h~1dffffh 0e8000h~0effffh ba37 l h h h h l * * * 1e0000h~1effffh 0f0000h~0f7fffh bk1 ba38 l h h h h h * * * 1f0000h~1fffffh 0f8000h~0fffffh ba39 h l l l l l * * * 200000h~20ffffh 100000h~107fffh ba40 h l l l l h * * * 210000h~21ffffh 108000h~10ffffh ba41 h l l l h l * * * 220000h~22ffffh 110000h~117fffh ba42 h l l l h h * * * 230000h~23ffffh 118000h~11ffffh ba43 h l l h l l * * * 240000h~24ffffh 120000h~127fffh ba44 h l l h l h * * * 250000h~25ffffh 128000h~12ffffh ba45 h l l h h l * * * 260000h~26ffffh 130000h~137fffh ba46 h l l h h h * * * 270000h~27ffffh 138000h~13ffffh ba47 h l h l l l * * * 280000h~28ffffh 140000h~147fffh ba48 h l h l l h * * * 290000h~29ffffh 148000h~14ffffh ba49 h l h l h l * * * 2a0000h~2affffh 150000h~157fffh ba50 h l h l h h * * * 2b0000h~2bffffh 158000h~15ffffh ba51 h l h h l l * * * 2c0000h~2cffffh 160000h~167fffh ba52 h l h h l h * * * 2d0000h~2dffffh 168000h~16ffffh ba53 h l h h h l * * * 2e0000h~2effffh 170000h~177fffh ba54 h l h h h h * * * 2f0000h~2fffffh 178000h~17ffffh ba55 h h l l l l * * * 300000h~30ffffh 180000h~187fffh ba56 h h l l l h * * * 310000h~31ffffh 188000h~18ffffh ba57 h h l l h l * * * 320000h~32ffffh 190000h~197fffh ba58 h h l l h h * * * 330000h~33ffffh 198000h~19ffffh ba59 h h l h l l * * * 340000h~34ffffh 1a0000h~1a7fffh ba60 h h l h l h * * * 350000h~35ffffh 1a8000h~1affffh ba61 h h l h h l * * * 360000h~36ffffh 1b0000h~1b7fffh bk2 ba62 h h l h h h * * * 370000h~37ffffh 1b8000h~1bffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 52/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba63 h h h l l l * * * 380000h~38ffffh 1c0000h~1c7fffh ba64 h h h l l h * * * 390000h~39ffffh 1c8000h~1cffffh ba65 h h h l h l * * * 3a0000h~3affffh 1d0000h~1d7fffh ba66 h h h l h h * * * 3b0000h~3bffffh 1d8000h~1dffffh ba67 h h h h l l * * * 3c0000h~3cffffh 1e0000h~1e7fffh ba68 h h h h l h * * * 3d0000h~3dffffh 1e8000h~1effffh ba69 h h h h h l * * * 3e0000h~3effffh 1f0000h~1f7fffh bk3 ba70 h h h h h h * * * 3fe000h~3fffffh 1f8000h~1fffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 53/63 (3) tc58fvm5t3a (top boot block) block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba0 l l l l l l * * * 000000h~00ffffh 000000h~007fffh ba1 l l l l l h * * * 010000h~01ffffh 008000h~00ffffh ba2 l l l l h l * * * 020000h~02ffffh 010000h~017fffh ba3 l l l l h h * * * 030000h~03ffffh 018000h~01ffffh ba4 l l l h l l * * * 040000h~04ffffh 020000h~027fffh ba5 l l l h l h * * * 050000h~05ffffh 028000h~02ffffh ba6 l l l h h l * * * 060000h~06ffffh 030000h~037fffh ba7 l l l h h h * * * 070000h~07ffffh 038000h~03ffffh ba8 l l h l l l * * * 080000h~08ffffh 040000h~047fffh ba9 l l h l l h * * * 090000h~09ffffh 048000h~04ffffh ba10 l l h l h l * * * 0a0000h~0affffh 050000h~057fffh ba11 l l h l h h * * * 0b0000h~0bffffh 058000h~05ffffh ba12 l l h h l l * * * 0c0000h~0cffffh 060000h~067fffh ba13 l l h h l h * * * 0d0000h~0dffffh 068000h~06ffffh ba14 l l h h h l * * * 0e0000h~0effffh 070000h~077fffh ba15 l l h h h h * * * 0f0000h~0fffffh 078000h~07ffffh ba16 l h l l l l * * * 100000h~10ffffh 080000h~087fffh ba17 l h l l l h * * * 110000h~11ffffh 088000h~08ffffh ba18 l h l l h l * * * 120000h~12ffffh 090000h~097fffh ba19 l h l l h h * * * 130000h~13ffffh 098000h~09ffffh ba20 l h l h l l * * * 140000h~14ffffh 0a0000h~0a7fffh ba21 l h l h l h * * * 150000h~15ffffh 0a8000h~0affffh ba22 l h l h h l * * * 160000h~16ffffh 0b0000h~0b7fffh bk0 ba23 l h l h h h * * * 170000h~17ffffh 0b8000h~0bffffh ba24 l h h l l l * * * 180000h~18ffffh 0c0000h~0c7fffh ba25 l h h l l h * * * 190000h~19ffffh 0c8000h~0cffffh ba26 l h h l h l * * * 1a0000h~1affffh 0d0000h~0d7fffh ba27 l h h l h h * * * 1b0000h~1bffffh 0d8000h~0dffffh ba28 l h h h l l * * * 1c0000h~1cffffh 0e0000h~0e7fffh ba29 l h h h l h * * * 1d0000h~1dffffh 0e8000h~0effffh ba30 l h h h h l * * * 1e0000h~1effffh 0f0000h~0f7fffh bk1 ba31 l h h h h h * * * 1f0000h~1fffffh 0f8000h~0fffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 54/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba32 h l l l l l * * * 200000h~20ffffh 100000h~107fffh ba33 h l l l l h * * * 210000h~21ffffh 108000h~10ffffh ba34 h l l l h l * * * 220000h~22ffffh 110000h~117fffh ba35 h l l l h h * * * 230000h~23ffffh 118000h~11ffffh ba36 h l l h l l * * * 240000h~24ffffh 120000h~127fffh ba37 h l l h l h * * * 250000h~25ffffh 128000h~12ffffh ba38 h l l h h l * * * 260000h~26ffffh 130000h~137fffh ba39 h l l h h h * * * 270000h~27ffffh 138000h~13ffffh ba40 h l h l l l * * * 280000h~28ffffh 140000h~147fffh ba41 h l h l l h * * * 290000h~29ffffh 148000h~14ffffh ba42 h l h l h l * * * 2a0000h~2affffh 150000h~157fffh ba43 h l h l h h * * * 2b0000h~2bffffh 158000h~15ffffh ba44 h l h h l l * * * 2c0000h~2cffffh 160000h~167fffh ba45 h l h h l h * * * 2d0000h~2dffffh 168000h~16ffffh ba46 h l h h h l * * * 2e0000h~2effffh 170000h~177fffh bk1 ba47 h l h h h h * * * 2f0000h~2fffffh 178000h~17ffffh ba48 h h l l l l * * * 300000h~30ffffh 180000h~187fffh ba49 h h l l l h * * * 310000h~31ffffh 188000h~18ffffh ba50 h h l l h l * * * 320000h~32ffffh 190000h~197fffh ba51 h h l l h h * * * 330000h~33ffffh 198000h~19ffffh ba52 h h l h l l * * * 340000h~34ffffh 1a0000h~1a7fffh ba53 h h l h l h * * * 350000h~35ffffh 1a8000h~1affffh ba54 h h l h h l * * * 360000h~36ffffh 1b0000h~1b7fffh bk2 ba55 h h l h h h * * * 370000h~37ffffh 1b8000h~1bffffh ba56 h h h l l l * * * 380000h~38ffffh 1c0000h~1c7fffh ba57 h h h l l h * * * 390000h~39ffffh 1c8000h~1cffffh ba58 h h h l h l * * * 3a0000h~3affffh 1d0000h~1d7fffh ba59 h h h l h h * * * 3b0000h~3bffffh 1d8000h~1dffffh ba60 h h h h l l * * * 3c0000h~3cffffh 1e0000h~1e7fffh ba61 h h h h l h * * * 3d0000h~3dffffh 1e8000h~1effffh bk3 ba62 h h h h h l * * * 3e0000h~3effffh 1f0000h~1f7fffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 55/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba63 h h h h l l l 3f0000h~3f1fffh 1f8000h~1f8fffh ba64 h h h h l l 3f2000h~3f3fffh 1f9000h~1f9fffh ba65 h h h h h h l h l 3f4000h~3f5fffh 1fa000h~1fafffh ba66 h h h h h h l h h 3f6000h~3f7fffh 1fb000h~1fbfffh ba67 h h h h h h h l l 3f8000h~3f9fffh 1fc000h~1fcfffh ba68 h h h h h h h l h 3fa000h~3fbfffh 1fd000h~1fdfffh ba69 h h h h h h h h l 3fc000h~3fdfffh 1fe000h~1fefffh bk3 ba70 h h h h h h h h h 3fe000h~3fffffh 1ff000h~1fffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 56/63 (4) tc58fvm5b3a (bottom boot block) block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba0 l l l l l l l l l 000000h~001fffh 000000h~000fffh ba1 l l l l l l l l h 002000h~003fffh 001000h~001fffh ba2 l l l l l l l h l 004000h~005fffh 002000h~002fffh ba3 l l l l l l l h h 006000h~007fffh 003000h~003fffh ba4 l l l l l l h l l 008000h~009fffh 004000h~004fffh ba5 l l l l l l h l h 00a000h~00bfffh 005000h~005fffh ba6 l l l l l l h h l 00c000h~00dfffh 006000h~006fffh ba7 l l l l l l h h h 00e000h~00ffffh 007000h~007fffh ba8 l l l l l h * * * 010000h~01ffffh 008000h~00ffffh ba9 l l l l h l * * * 020000h~02ffffh 010000h~017fffh ba10 l l l l h h * * * 030000h~03ffffh 018000h~01ffffh ba11 l l l h l l * * * 040000h~04ffffh 020000h~027fffh ba12 l l l h l h * * * 050000h~05ffffh 028000h~02ffffh ba13 l l l h h l * * * 060000h~06ffffh 030000h~037fffh bk0 ba14 l l l h h h * * * 070000h~07ffffh 038000h~03ffffh ba15 l l h l l l * * * 080000h~08ffffh 040000h~047fffh ba16 l l h l l h * * * 090000h~09ffffh 048000h~04ffffh ba17 l l h l h l * * * 0a0000h~0affffh 050000h~057fffh ba18 l l h l h h * * * 0b0000h~0bffffh 058000h~05ffffh ba19 l l h h l l * * * 0c0000h~0cffffh 060000h~067fffh ba20 l l h h l h * * * 0d0000h~0dffffh 068000h~06ffffh ba21 l l h h h l * * * 0e0000h~0effffh 070000h~077fffh bk1 ba22 l l h h h h * * * 0f0000h~0fffffh 078000h~07ffffh ba23 l h l l l l * * * 100000h~10ffffh 080000h~087fffh ba24 l h l l l h * * * 110000h~11ffffh 088000h~08ffffh ba25 l h l l h l * * * 120000h~12ffffh 090000h~097fffh ba26 l h l l h h * * * 130000h~13ffffh 098000h~09ffffh ba27 l h l h l l * * * 140000h~14ffffh 0a0000h~0a7fffh ba28 l h l h l h * * * 150000h~15ffffh 0a8000h~0affffh ba29 l h l h h l * * * 160000h~16ffffh 0b0000h~0b7fffh bk2 ba30 l h l h h h * * * 170000h~17ffffh 0b8000h~0bffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 57/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba31 l h h l l l * * * 180000h~18ffffh 0c0000h~0c7fffh ba32 l h h l l h * * * 190000h~19ffffh 0c8000h~0cffffh ba33 l h h l h l * * * 1a0000h~1affffh 0d0000h~0d7fffh ba34 l h h l h h * * * 1b0000h~1bffffh 0d8000h~0dffffh ba35 l h h h l l * * * 1c0000h~1cffffh 0e0000h~0e7fffh ba36 l h h h l h * * * 1d0000h~1dffffh 0e8000h~0effffh ba37 l h h h h l * * * 1e0000h~1effffh 0f0000h~0f7fffh ba38 l h h h h h * * * 1f0000h~1fffffh 0f8000h~0fffffh ba39 h l l l l l * * * 200000h~20ffffh 100000h~107fffh ba40 h l l l l h * * * 210000h~21ffffh 108000h~10ffffh ba41 h l l l h l * * * 220000h~22ffffh 110000h~117fffh ba42 h l l l h h * * * 230000h~23ffffh 118000h~11ffffh ba43 h l l h l l * * * 240000h~24ffffh 120000h~127fffh ba44 h l l h l h * * * 250000h~25ffffh 128000h~12ffffh ba45 h l l h h l * * * 260000h~26ffffh 130000h~137fffh bk2 ba46 h l l h h h * * * 270000h~27ffffh 138000h~13ffffh ba47 h l h l l l * * * 280000h~28ffffh 140000h~147fffh ba48 h l h l l h * * * 290000h~29ffffh 148000h~14ffffh ba49 h l h l h l * * * 2a0000h~2affffh 150000h~157fffh ba50 h l h l h h * * * 2b0000h~2bffffh 158000h~15ffffh ba51 h l h h l l * * * 2c0000h~2cffffh 160000h~167fffh ba52 h l h h l h * * * 2d0000h~2dffffh 168000h~16ffffh ba53 h l h h h l * * * 2e0000h~2effffh 170000h~177fffh ba54 h l h h h h * * * 2f0000h~2fffffh 178000h~17ffffh ba55 h h l l l l * * * 300000h~30ffffh 180000h~187fffh ba56 h h l l l h * * * 310000h~31ffffh 188000h~18ffffh ba57 h h l l h l * * * 320000h~32ffffh 190000h~197fffh ba58 h h l l h h * * * 330000h~33ffffh 198000h~19ffffh ba59 h h l h l l * * * 340000h~34ffffh 1a0000h~1a7fffh ba60 h h l h l h * * * 350000h~35ffffh 1a8000h~1affffh ba61 h h l h h l * * * 360000h~36ffffh 1b0000h~1b7fffh bk3 ba62 h h l h h h * * * 370000h~37ffffh 1b8000h~1bffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 58/63 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba63 h h h l l l * * * 380000h~38ffffh 1c0000h~1c7fffh ba64 h h h l l h * * * 390000h~39ffffh 1c8000h~1cffffh ba65 h h h l h l * * * 3a0000h~3affffh 1d0000h~1d7fffh ba66 h h h l h h * * * 3b0000h~3bffffh 1d8000h~1dffffh ba67 h h h h l l * * * 3c0000h~3cffffh 1e0000h~1e7fffh ba68 h h h h l h * * * 3d0000h~3dffffh 1e8000h~1effffh ba69 h h h h h l * * * 3e0000h~3effffh 1f0000h~1f7fffh bk3 ba70 h h h h h h * * * 3fe000h~3fffffh 1f8000h~1fffffh
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 59/63 block size table (1) tc58fvm5t2a (top boot block) block size bank size block # byte mode word mode bank # byte mode word mode block count ba0~ba7 64 kbytes 32 kwords bk0 512 kbytes 256 kwords 8 ba8~ba31 64 kbytes 32 kwords bk1 1536 kbytes 768 kwords 24 ba32~ba55 64 kbytes 32 kwords bk2 1536 kbytes 768 kwords 24 ba56~ba62 64 kbytes 32 kwords bk3 448 kbytes 224 kwords 7 ba63~ba70 8 kbytes 4 kwords bk3 64 kbytes 32 kwords 8 (2) TC58FVM5B2A (bottom boot block) block size bank size block # byte mode word mode bank # byte mode word mode block count ba0~ba7 8 kbytes 4 kwords bk0 64 kbytes 32 kbytes 8 ba8~ba14 64 kbytes 32 kwords bk0 448 kbytes 224 kwords 7 ba15~ba38 64 kbytes 32 kwords bk1 1536 kbytes 768 kwords 24 ba39~ba62 64 kbytes 32 kwords bk2 1536 kbytes 768 kwords 24 ba63~ba70 64 kbytes 32 kwords bk3 512 kbytes 256 kwords 8 (3) tc58fvm5t3a (top boot block) block size bank size block # byte mode word mode bank # byte mode word mode block count ba0~ba23 64 kbytes 32 kwords bk0 1536 kbytes 768 kwords 24 ba24~ba47 64 kbytes 32 kwords bk1 1536 kbytes 768 kwords 24 ba48~ba55 64 kbytes 32 kwords bk2 512 kbytes 256 kwords 8 ba56~ba62 64 kbytes 32 kwords bk3 448 kbytes 224 kwords 7 ba63~ba70 8 kbytes 4 kwords bk3 64 kbytes 32 kwords 8 (4) tc58fvm5b3a (bottom boot block) block size bank size block # byte mode word mode bank # byte mode word mode block count ba0~ba7 8 kbytes 4 kwords bk0 64 kbytes 32 kbytes 8 ba8~ba14 64 kbytes 32 kwords bk0 448 kbytes 224 kwords 7 ba15~ba22 64 kbytes 32 kwords bk1 512 kbytes 256 kwords 8 ba23~ba46 64 kbytes 32 kwords bk2 1536 kbytes 768 kwords 24 ba47~ba70 64 kbytes 32 kwords bk3 1536 kbytes 768 kwords 24
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 60/63 package dimensions unit: mm
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 61/63 package dimensions unit: mm b a ll s i de
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 62/63 revision history date version description 2002- 06-20 1.00 original version 2002- 07-31 1.01 added v id /v acc comments. 2002- 08-06 1.02 added i ddo8 . 2002- 08-26 1.03 added dc typical value. 2002- 09-10 1.04 added fbga package. added ordering information. 2002-10-24 1.05 generalize
tc58fvm5(t/b)(2/3)a(ft/xb)65 2002-10-24 63/63 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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